In existing core switching networks, multistage interconnected cluster technology is mostly adopted to implement a high-performance router for a network with switching capacity of over T bits. Such high-performance router is mainly applied in a backbone network to provide excellent Quality of Service (QoS) performance, with the typical structure as shown in FIG. 1. It can be seen that an SF chip is in two working modes in a two-stage interconnected network.
In the first working mode, the SF chip is on a cascadable rack and is connected with a Switch Access (SA) chip and an SF chip of the next stage. The working mode is logically divided into two procedures: firstly, a cell is obtained from the SA chip to be switched to the SF chip of the next stage; and then, the cell is obtained from the SF chip of the next stage to be switched to the SA chip. The two procedures are referred to as SF1 and SF3 respectively and the first working mode is referred to as SF13 mode.
In the second working mode, the SF chip is on a cascaded rack and a cell is obtained in the SF1 and is then switched in the SF3. The second mode is referred to as SF2 mode.
In the two working modes, the SF chip processes the cell differently. In order to enable the SF chip to adapt to different working modes, it is necessary to set a processing circuit for each working mode of the SF chip independently. However, this may affect the scale and power consumption of the chip as well as reliability of the chip.